PM-16 Micro-CPU

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The instruction set

The top five bits are the opcode, and the opcode alone selects the format. Flag column: none writes no flags · add unsigned carry-out · sub carry means borrow · log clears CF and OF · shf CF is the last bit shifted out.

Condition codes

One opcode, sixteen predicates over the flags already computed. Every code is defined; there is no illegal encoding.

Programmer's model

Registers

R0–R7, fully general; none is hardwired to zero

Special

PC · SP · IR, each 16 bits

Flags

ZF (zero) · SF (sign) · CF (carry/borrow) · OF (signed overflow)

Memory

65,536 words of 16 bits; one address is one word, so there is no alignment rule and no endianness inside the machine

RAM

0x0000–0xEFFF, shared by code, data and stack

Reserved

0xF000–0xF7FF, held for a future framebuffer

Console MMIO

0xF800–0xFFFF: 32 rows × 64 columns, cell (row, col) at 0xF800 + row×64 + col

Stack

full-descending; SP resets to 0xF000 and the first PUSH writes 0xEFFF

Entry point

always 0x0000

Worked example: Fibonacci

The first sample program writes the first twelve Fibonacci numbers to memory and halts after exactly 90 steps.

; fib.asm: the first 12 Fibonacci numbers into 0x0200..0x020B
        .equ  COUNT, 12
        .equ  DEST,  0x0200

        .org  0x0000
start:  SET   R3, #DEST         ; R3 = write pointer
        LDL   R0, #0            ; R0 = a
        LDL   R1, #1            ; R1 = b
        LDL   R4, #COUNT        ; R4 = counter
loop:   ST    R0, [R3]          ; mem[p] = a
        ADDI  R3, R3, #1        ; p = p + 1
        ADD   R2, R0, R1        ; t = a + b
        MOV   R0, R1            ; a = b
        MOV   R1, R2            ; b = t
        ADDI  R4, R4, #-1       ; counter = counter - 1
        BRNE  loop              ; ZF from the ADDI
        HALT

Assembled

segment @ 0000: 13 words
  0000  DB00  LDL R3, #0x00
  0001  E302  LDH R3, #0x02
  0002  D800  LDL R0, #0x00
  0003  D901  LDL R1, #0x01
  0004  DC0C  LDL R4, #0x0C
  0005  D060  ST R0, [R3 + #0]
  0006  BB61  ADDI R3, R3, #1
  0007  1204  ADD R2, R0, R1
  0008  5820  MOV R0, R1
  0009  5940  MOV R1, R2
  000A  BC9F  ADDI R4, R4, #-1
  000B  E9F9  BRNE .-7
  000C  0000  HALT

Trace

The first 24 of 90 steps, two full turns of the loop. Flags after is dimmed where the instruction writes no flags at all, which is most of them: only the sixteen ALU instructions touch the flags, which is what lets you compare, then load, then branch.

At halt

The last ADDI R4, R4, #-1 computed 0x0001 + 0xFFFF, which carried, so the machine halts with CF set even though the loop counted down to zero. ADDI is an addition, so its carry is an add-carry, the opposite polarity from SUB and CMPI. There is no SUBI; that is deliberate, and it is the first thing to try predicting.

result: halted after 90 steps
PC=000D  SP=F000  IR=0000  Z=1 S=0 C=1 O=0  steps=90  HALTED
R0=0090  R1=00E9  R2=00E9  R3=020C
R4=0000  R5=0000  R6=0000  R7=0000
min SP: F000
memory writes: 12
digest: 31965eb81e41eb20d062558b4e6f4d5968c59c83f4300cc2e174e617e521c8d3
segments:
  0000: 13 words
console row 0: ||

cargo build --release --bin cpu-cli